From 5fb4e2d02e916a9ef3cc821f7f64d6d96d5f87bf Mon Sep 17 00:00:00 2001 From: Chao Shi Date: Sun, 14 Jun 2026 13:15:35 +0800 Subject: [PATCH] [UnifiedTree] Use Qwen3-32B in unified radix pp kl tests and set KL threshold to 0.005 (#27931) --- .../test_unified_radix_cache_hicache_pp_kl.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/test/registered/radix_cache/unified_radix_tree/test_unified_radix_cache_hicache_pp_kl.py b/test/registered/radix_cache/unified_radix_tree/test_unified_radix_cache_hicache_pp_kl.py index 6e6068404..4ee60cc58 100644 --- a/test/registered/radix_cache/unified_radix_tree/test_unified_radix_cache_hicache_pp_kl.py +++ b/test/registered/radix_cache/unified_radix_tree/test_unified_radix_cache_hicache_pp_kl.py @@ -15,7 +15,7 @@ from sglang.test.test_utils import ( register_cuda_ci(est_time=400, stage="base-c", runner_config="4-gpu-h100") -QWEN3_30B_MODEL = "Qwen/Qwen3-30B-A3B-FP8" +QWEN3_32B_MODEL = "Qwen/Qwen3-32B" def _assert_pp_decode_cached_tokens(result, history_len, output_len, label): @@ -28,12 +28,12 @@ def _assert_pp_decode_cached_tokens(result, history_len, output_len, label): class TestUnifiedQwen3HiCachePP(UnifiedRadixTreeTestMixin, CustomTestCase): - """Qwen3-30B-A3B-FP8 + HiCache + PP + UnifiedRadixCache.""" + """Qwen3-32B + HiCache + PP + UnifiedRadixCache.""" hicache_io_backend = "direct" hicache_mem_layout = "page_first_direct" max_running_requests = 2 - kl_threshold = 0.012 + kl_threshold = 0.005 gsm8k_threshold = 0.7 num_gsm8k_questions = 50 mmlu_threshold = 0.7 @@ -61,7 +61,7 @@ class TestUnifiedQwen3HiCachePP(UnifiedRadixTreeTestMixin, CustomTestCase): @classmethod def setUpClass(cls): - cls.model = QWEN3_30B_MODEL + cls.model = QWEN3_32B_MODEL cls.base_url = DEFAULT_URL_FOR_TEST cls.process = popen_launch_server( cls.model,