[PP][DeepSeek V4] Overlap communication and optimize SM120 prefill (#38792)
Co-authored-by: Yangmin Li <yangminl@nvidia.com> Co-authored-by: YAMY <74099316+YAMY1234@users.noreply.github.com>
This commit is contained in:
co-authored by
Yangmin Li
YAMY
parent
929230a6f0
commit
5e9342d16f
@@ -14,6 +14,7 @@ from sglang.srt.mem_cache.deepseek_v4_memory_pool import (
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DeepSeekV4SingleKVPool,
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DeepSeekV4TokenToKVPool,
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_CompressedPoolConfig,
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_num_dsv4_physical_kv_pages,
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)
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from sglang.srt.runtime_context import get_context
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from sglang.test.ci.ci_register import register_cpu_ci
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@@ -23,6 +24,40 @@ register_cpu_ci(est_time=5, suite="base-a-test-cpu")
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class TestDSV4CompressedPools(CustomTestCase):
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def test_physical_kv_pages_cover_reserved_logical_page(self):
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size = 8192
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self.assertEqual(_num_dsv4_physical_kv_pages(size, 256, 256), 33)
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self.assertEqual(_num_dsv4_physical_kv_pages(size, 64, 256), 132)
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self.assertGreaterEqual(
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_num_dsv4_physical_kv_pages(size, 64, 256) * 64,
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size + 256,
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)
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def test_state_buf_item_covers_one_logical_swa_page(self):
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pool = DeepSeekV4TokenToKVPool.__new__(DeepSeekV4TokenToKVPool)
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pool._unified_kv = False
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pool.swa_page_size = 256
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pool.compress_state_pools = []
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pool.indexer_compress_state_pools = []
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for physical_page_size in (256, 64):
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with self.subTest(physical_page_size=physical_page_size):
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row_bytes = physical_page_size * 4
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buf = torch.empty((8, row_bytes), dtype=torch.uint8)
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pool.swa_kv_pool = SimpleNamespace(
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page_size=physical_page_size, kv_buffer=[buf]
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)
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data_ptrs, data_lens, item_lens = pool.get_state_buf_infos()
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self.assertEqual(data_ptrs, [buf.data_ptr()])
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self.assertEqual(data_lens, [buf.nbytes])
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self.assertEqual(item_lens, [256 * 4])
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def test_state_buf_infos_without_paged_swa(self):
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pool = DeepSeekV4TokenToKVPool.__new__(DeepSeekV4TokenToKVPool)
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pool.swa_kv_pool = None
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pool.compress_state_pools = []
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pool.indexer_compress_state_pools = []
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self.assertEqual(pool.get_state_buf_infos(), ([], [], []))
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def test_pp_mapping_and_pd_buffer_order(self):
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for unified, stage_ratios in product(
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(False, True), ([4, 0, 128, 4], [128], [0])
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@@ -11,6 +11,7 @@ from sglang.srt.mem_cache.hybrid_cache.hybrid_pool_assembler import (
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_evict_swa_for_device_alloc,
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_MambaStrategy,
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_MambaSwaStrategy,
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_require_single_row_dsv4_swa_pages,
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_split_hicache_size,
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_SwaStrategy,
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build_full_draft_pools,
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@@ -22,6 +23,23 @@ from sglang.test.test_utils import CustomTestCase
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register_cpu_ci(est_time=11, suite="base-a-test-cpu")
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class TestDeepSeekV4SWAPageLayout(CustomTestCase):
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def test_split_physical_rows_are_rejected_for_hicache_consumers(self):
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with self.assertRaisesRegex(ValueError, "direct SWA KV layout"):
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_require_single_row_dsv4_swa_pages(
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logical_page_size=256,
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physical_page_size=64,
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consumer="test consumer",
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)
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def test_matching_page_geometry_is_supported(self):
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_require_single_row_dsv4_swa_pages(
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logical_page_size=256,
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physical_page_size=256,
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consumer="test consumer",
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)
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class _Pool:
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def __init__(self, kv_bytes):
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self._kv_bytes = kv_bytes
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@@ -179,7 +179,8 @@ class TestHybridDevicePoolAssembler(CustomTestCase):
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kvcache.end_layer = 4
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kvcache.swa_page_size = 2
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kvcache.swa_kv_pool = SimpleNamespace(
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kv_buffer=[torch.zeros((8, 3), dtype=torch.uint8) for _ in range(3)]
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page_size=2,
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kv_buffer=[torch.zeros((8, 3), dtype=torch.uint8) for _ in range(3)],
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)
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kvcache.c4_kv_pool = SimpleNamespace(
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kv_buffer=[torch.zeros((8, 5), dtype=torch.uint8) for _ in range(2)],
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