[core] Don't force seq_lens_cpu publication under piecewise CUDA graph (#28633)
Co-authored-by: jonnykong <jonnykong@fb.com> Co-authored-by: Liangsheng Yin <hnyls2002@gmail.com> Co-authored-by: hnyls2002 <lsyincs@gmail.com>
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co-authored by
jonnykong
Liangsheng Yin
hnyls2002
parent
d271de64fe
commit
3ed46f599f
@@ -5,7 +5,7 @@ from typing import TYPE_CHECKING, Sequence, Union
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import torch
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import torch
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from sglang.srt.environ import envs
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from sglang.srt.environ import envs
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from sglang.srt.model_executor.cuda_graph_config import Backend
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from sglang.srt.speculative.spec_info import SpeculativeAlgorithm
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from sglang.srt.speculative.spec_utils import spec_need_hidden_states
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from sglang.srt.speculative.spec_utils import spec_need_hidden_states
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from sglang.srt.speculative.triton_ops.gather_spec_extras import gather_spec_extras
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from sglang.srt.speculative.triton_ops.gather_spec_extras import gather_spec_extras
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from sglang.srt.utils import is_cuda, is_hip, is_npu
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from sglang.srt.utils import is_cuda, is_hip, is_npu
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@@ -16,7 +16,6 @@ if TYPE_CHECKING:
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from sglang.srt.mem_cache.memory_pool import ReqToTokenPool
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from sglang.srt.mem_cache.memory_pool import ReqToTokenPool
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from sglang.srt.server_args import ServerArgs
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from sglang.srt.server_args import ServerArgs
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from sglang.srt.speculative.eagle_info import EagleDraftInput
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from sglang.srt.speculative.eagle_info import EagleDraftInput
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from sglang.srt.speculative.spec_info import SpeculativeAlgorithm
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def decide_needs_cpu_seq_lens(
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def decide_needs_cpu_seq_lens(
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@@ -25,18 +24,16 @@ def decide_needs_cpu_seq_lens(
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) -> bool:
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) -> bool:
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"""Whether FutureMap must publish seq_lens_cpu / sum.
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"""Whether FutureMap must publish seq_lens_cpu / sum.
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OR over per-backend needs_cpu_seq_lens; force True under TBO / piecewise CG
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OR over per-backend needs_cpu_seq_lens; force True under TBO (it reads the
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(they read the CPU mirror outside the backend layer).
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CPU mirror outside the backend layer to split the batch) or ngram (its
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USE_FULL_MASK verify path reads the host mirror regardless of backend).
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"""
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"""
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if server_args.enable_two_batch_overlap:
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if server_args.enable_two_batch_overlap:
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# FIXME: support TBO without seq lens cpu value
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# FIXME: support TBO without seq lens cpu value
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return True
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return True
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cuda_graph_config = server_args.cuda_graph_config
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if SpeculativeAlgorithm.from_string(server_args.speculative_algorithm).is_ngram():
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if (
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# ngram's USE_FULL_MASK verify path reads seq_lens_cpu per req to size
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cuda_graph_config is not None
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# the tree mask, regardless of the attn backend (e.g. Triton opts out).
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and cuda_graph_config.prefill.backend == Backend.TC_PIECEWISE
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):
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# FIXME: support PCG without seq lens cpu value
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return True
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return True
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# Skip unset slots (e.g. draft_extend_attn_backend on some spec configs);
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# Skip unset slots (e.g. draft_extend_attn_backend on some spec configs);
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# missing flag -> True so undeclared backends stay on the legacy path.
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# missing flag -> True so undeclared backends stay on the legacy path.
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@@ -1009,19 +1009,6 @@ class TestPrefillOnlyDisableKvCache(unittest.TestCase):
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class TestCudaGraphConfigDataclassAccess(CustomTestCase):
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class TestCudaGraphConfigDataclassAccess(CustomTestCase):
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def test_overlap_force_cpu_seq_lens_with_tc_piecewise_prefill(self):
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from sglang.srt.managers.overlap_utils import decide_needs_cpu_seq_lens
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server_args = SimpleNamespace(
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enable_two_batch_overlap=False,
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cuda_graph_config=CudaGraphConfig(
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prefill=PhaseConfig(backend=Backend.TC_PIECEWISE)
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),
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)
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attn_backend = SimpleNamespace(needs_cpu_seq_lens=False)
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self.assertTrue(decide_needs_cpu_seq_lens(server_args, [attn_backend]))
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@patch(
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@patch(
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"sglang.srt.model_executor.runner_backend."
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"sglang.srt.model_executor.runner_backend."
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"tc_piecewise_cuda_graph_backend.get_moe_a2a_backend"
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"tc_piecewise_cuda_graph_backend.get_moe_a2a_backend"
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