From 24d15dd92e2caf861f54706e849afdb060ee32e6 Mon Sep 17 00:00:00 2001 From: billishyahao Date: Fri, 19 Jun 2026 12:26:48 +0800 Subject: [PATCH] [AMD][DSV4] fix nonetype issue when enabling hicache (#28541) --- python/sglang/srt/environ.py | 1 + python/sglang/srt/server_args.py | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/python/sglang/srt/environ.py b/python/sglang/srt/environ.py index cea221453..eb2027bdf 100644 --- a/python/sglang/srt/environ.py +++ b/python/sglang/srt/environ.py @@ -475,6 +475,7 @@ class Envs: # Enable dual-stream MoE (shared experts vs routed experts) on the # ROCm/AITER path. Requires GPU_MAX_HW_QUEUES>=5 to avoid HW-queue serialization. SGLANG_ROCM_USE_MULTI_STREAM = EnvBool(False) + SGLANG_HACK_FLASHMLA_BACKEND = EnvStr("tilelang") # MPS (Apple Silicon) SGLANG_USE_MLX = EnvBool(False) diff --git a/python/sglang/srt/server_args.py b/python/sglang/srt/server_args.py index 69ca84f87..882360b4b 100644 --- a/python/sglang/srt/server_args.py +++ b/python/sglang/srt/server_args.py @@ -3982,6 +3982,26 @@ class ServerArgs: # Step 2: Storage-layout normalization without changing io backend. self._resolve_storage_layout_compatibility() + # Step 3: HiCache is not yet supported with the DeepSeek-V4 hip unified_kv + # layout, so fall back to the default tilelang FlashMLA backend. + self._resolve_unified_kv_hicache_compatibility() + + def _resolve_unified_kv_hicache_compatibility(self): + # The DeepSeek-V4 unified_kv layout (SGLANG_HACK_FLASHMLA_BACKEND= + # unified_kv_triton) keeps swa/c4/c128 in a single per-layer buffer and + # has no HiCache host-pool support yet, so reset the backend to the + # default (tilelang) so the server still starts. + if not self.enable_hierarchical_cache: + return + + if envs.SGLANG_HACK_FLASHMLA_BACKEND.get() == "unified_kv_triton": + envs.SGLANG_HACK_FLASHMLA_BACKEND.set("tilelang") + logger.warning( + "SGLANG_HACK_FLASHMLA_BACKEND=unified_kv_triton is not yet " + "compatible with --enable-hierarchical-cache; falling back to " + "SGLANG_HACK_FLASHMLA_BACKEND=tilelang." + ) + def _resolve_layout_io_compatibility(self): if ( self.hicache_mem_layout == "page_first_direct"