Fix DSV4 HiSparse SWA tail allocation forwarding (#30408)
Co-authored-by: Zhangheng <hzh0425@apache.org>
This commit is contained in:
@@ -68,10 +68,7 @@ from sglang.srt.managers.schedule_batch import (
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from sglang.srt.managers.schedule_policy import match_prefix_for_req
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from sglang.srt.managers.utils import GenerationBatchResult
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from sglang.srt.mem_cache.allocator import BaseTokenToKVPoolAllocator
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from sglang.srt.mem_cache.base_prefix_cache import (
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BasePrefixCache,
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EvictParams,
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)
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from sglang.srt.mem_cache.base_prefix_cache import BasePrefixCache, EvictParams
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from sglang.srt.mem_cache.common import (
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kv_to_page_indices,
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page_align_floor,
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@@ -1285,11 +1282,15 @@ class DecodePreallocQueue(DecodeHiCachePreallocMixin):
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)
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if self.scheduler.enable_hisparse:
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# HiSparse pre-alloc only allocates logical indices (alloc_logical_only),
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# so the logical pool is the binding constraint for admission control.
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available_size = (
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self.token_to_kv_pool_allocator.logical_attn_allocator.available_size()
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)
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logical_allocator = self.token_to_kv_pool_allocator.logical_attn_allocator
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if self._uses_swa_tail_prealloc() and hasattr(
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logical_allocator, "full_available_size"
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):
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available_size = logical_allocator.full_available_size()
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else:
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# HiSparse pre-alloc only allocates logical indices, so the
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# logical pool is the binding constraint for admission control.
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available_size = logical_allocator.available_size()
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elif self._uses_swa_tail_prealloc():
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available_size = self.token_to_kv_pool_allocator.full_available_size()
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if self.scheduler.server_args.disaggregation_decode_enable_radix_cache:
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@@ -1471,14 +1472,32 @@ class DecodePreallocQueue(DecodeHiCachePreallocMixin):
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# device indices) and allocate host indices for RDMA destination.
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coordinator = self.scheduler.hisparse_coordinator
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device = self.token_to_kv_pool_allocator.device
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kv_loc = self.token_to_kv_pool_allocator.alloc_logical_only(
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prefix_lens=torch.tensor([0], dtype=torch.int64, device=device),
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prefix_lens_cpu=torch.tensor([0], dtype=torch.int64),
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seq_lens=torch.tensor([fill_len], dtype=torch.int64, device=device),
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seq_lens_cpu=torch.tensor([fill_len], dtype=torch.int64),
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last_loc=torch.tensor([-1], dtype=torch.int64, device=device),
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extend_num_tokens=fill_len,
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)
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prefix_lens = torch.tensor([0], dtype=torch.int64, device=device)
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prefix_lens_cpu = torch.tensor([0], dtype=torch.int64)
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seq_lens = torch.tensor([fill_len], dtype=torch.int64, device=device)
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seq_lens_cpu = torch.tensor([fill_len], dtype=torch.int64)
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last_loc = torch.tensor([-1], dtype=torch.int64, device=device)
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if self._uses_swa_tail_prealloc():
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swa_tail_len = self._swa_tail_len(fill_len)
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kv_loc = self.token_to_kv_pool_allocator.alloc_extend_swa_tail(
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prefix_lens=prefix_lens,
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prefix_lens_cpu=prefix_lens_cpu,
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seq_lens=seq_lens,
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seq_lens_cpu=seq_lens_cpu,
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last_loc=last_loc,
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extend_num_tokens=fill_len,
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swa_tail_len=swa_tail_len,
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)
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req.swa_evicted_seqlen = fill_len - swa_tail_len
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else:
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kv_loc = self.token_to_kv_pool_allocator.alloc_logical_only(
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prefix_lens=prefix_lens,
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prefix_lens_cpu=prefix_lens_cpu,
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seq_lens=seq_lens,
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seq_lens_cpu=seq_lens_cpu,
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last_loc=last_loc,
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extend_num_tokens=fill_len,
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)
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# Allocate host indices for the RDMA transfer target.
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host_indices = coordinator.mem_pool_host.alloc_paged_token_slots(
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@@ -402,6 +402,26 @@ class DeepSeekV4HiSparseTokenToKVPoolAllocator(BaseTokenToKVPoolAllocator):
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extend_num_tokens,
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)
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def alloc_extend_swa_tail(
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self,
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prefix_lens: torch.Tensor,
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prefix_lens_cpu: torch.Tensor,
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seq_lens: torch.Tensor,
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seq_lens_cpu: torch.Tensor,
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last_loc: torch.Tensor,
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extend_num_tokens: int,
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swa_tail_len: int,
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):
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return self.logical_attn_allocator.alloc_extend_swa_tail(
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prefix_lens=prefix_lens,
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prefix_lens_cpu=prefix_lens_cpu,
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seq_lens=seq_lens,
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seq_lens_cpu=seq_lens_cpu,
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last_loc=last_loc,
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extend_num_tokens=extend_num_tokens,
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swa_tail_len=swa_tail_len,
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)
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def alloc_device_buffer(self, allocated_indices, need_size: int):
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assert need_size % self.hisparse_page_size == 0
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hisparse_indices = self.full_to_hisparse_device_index_mapping[allocated_indices]
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