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[HiCache][AMD] Add UMBP tiered DRAM + SSD L3 storage backend with hugepage host allocator (#25377)

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Co-authored-by: TianDi101 ditian12@amd.com
Co-authored-by: Niko Ma nima@amd.com
Co-authored-by: Wu, Yutong yutong.wu@amd.com
Co-authored-by: figo fizhang@amd.com
Co-authored-by: AMD-yanfeiwang <yanfei.wang@amd.com>
Co-authored-by: Zhangheng <hzh0425@apache.org>
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inkcherry
2026-07-01 22:21:37 +08:00
committed by GitHub
co-authored by TianDi101 ditian12@amd.com Niko Ma nima@amd.com Wu, Yutong yutong.wu@amd.com figo fizhang@amd.com AMD-yanfeiwang Zhangheng
parent a0d9791810
commit 13dc5f2dc7
9 changed files with 2106 additions and 1 deletions
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python/sglang/srt/managers/cache_controller.py
+1 -1
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@@ -483,7 +483,7 @@ class HiCacheController:
if (
self.storage_backend_type
in ["hf3fs", "mooncake", "eic", "nixl", "simm"]
in ["hf3fs", "mooncake", "eic", "nixl", "simm", "mori"]
) or (
self.storage_backend_type == "dynamic"
and bool(self.storage_config.extra_config.get("interface_v1", 0))