docs: update checkpoint to Qwen3.5 NVFP4 V2 for InfX (#32945)
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@@ -42,7 +42,7 @@ Qwen3.5 features a Gated Delta Networks combined with sparse Mixture-of-Experts
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<td style={{padding: "9px 12px", fontWeight: 500, backgroundColor: "rgba(255,255,255,0.02)"}}>Qwen3.5-397B-A17B</td>
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<td style={{padding: "9px 12px", fontWeight: 500, backgroundColor: "rgba(255,255,255,0.02)"}}>Qwen3.5-397B-A17B</td>
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<td style={{padding: "9px 12px", backgroundColor: "rgba(255,255,255,0.05)"}}>[Qwen/Qwen3.5-397B-A17B](https://huggingface.co/Qwen/Qwen3.5-397B-A17B)</td>
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<td style={{padding: "9px 12px", backgroundColor: "rgba(255,255,255,0.05)"}}>[Qwen/Qwen3.5-397B-A17B](https://huggingface.co/Qwen/Qwen3.5-397B-A17B)</td>
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<td style={{padding: "9px 12px", backgroundColor: "rgba(255,255,255,0.02)"}}>[Qwen/Qwen3.5-397B-A17B-FP8](https://huggingface.co/Qwen/Qwen3.5-397B-A17B-FP8)</td>
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<td style={{padding: "9px 12px", backgroundColor: "rgba(255,255,255,0.02)"}}>[Qwen/Qwen3.5-397B-A17B-FP8](https://huggingface.co/Qwen/Qwen3.5-397B-A17B-FP8)</td>
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<td style={{padding: "9px 12px", backgroundColor: "rgba(255,255,255,0.05)"}}>NVIDIA NVFP4: [nvidia/Qwen3.5-397B-A17B-NVFP4](https://huggingface.co/nvidia/Qwen3.5-397B-A17B-NVFP4)<br/>AMD MXFP4: [amd/Qwen3.5-397B-A17B-MXFP4](https://huggingface.co/amd/Qwen3.5-397B-A17B-MXFP4)</td>
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<td style={{padding: "9px 12px", backgroundColor: "rgba(255,255,255,0.05)"}}>NVIDIA NVFP4: [nvidia/Qwen3.5-397B-A17B-NVFP4-V2](https://huggingface.co/nvidia/Qwen3.5-397B-A17B-NVFP4-V2)<br/>AMD MXFP4: [amd/Qwen3.5-397B-A17B-MXFP4](https://huggingface.co/amd/Qwen3.5-397B-A17B-MXFP4)</td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td style={{padding: "9px 12px", fontWeight: 500, backgroundColor: "rgba(255,255,255,0.02)"}}>Qwen3.5-122B-A10B</td>
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<td style={{padding: "9px 12px", fontWeight: 500, backgroundColor: "rgba(255,255,255,0.02)"}}>Qwen3.5-122B-A10B</td>
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@@ -156,7 +156,7 @@ This section provides deployment configurations optimized for different hardware
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- **MI300X (192GB)** runs with tp=4.
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- **MI300X (192GB)** runs with tp=4.
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- **MI325X (256GB)** runs with tp=2.
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- **MI325X (256GB)** runs with tp=2.
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- **MI355X (288GB)** runs with tp=2.
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- **MI355X (288GB)** runs with tp=2.
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- **FP4**: The FP4 quantized model requires ~250GB for weights, cutting memory by almost 4x. NVFP4 ([nvidia/Qwen3.5-397B-A17B-NVFP4](https://huggingface.co/nvidia/Qwen3.5-397B-A17B-NVFP4)) requires B200/B300 (Blackwell architecture); AMD provides an MXFP4 checkpoint ([amd/Qwen3.5-397B-A17B-MXFP4](https://huggingface.co/amd/Qwen3.5-397B-A17B-MXFP4)) for MI355X.
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- **FP4**: The FP4 quantized model requires ~250GB for weights, cutting memory by almost 4x. NVFP4 ([nvidia/Qwen3.5-397B-A17B-NVFP4-V2](https://huggingface.co/nvidia/Qwen3.5-397B-A17B-NVFP4-V2)) requires B200/B300 (Blackwell architecture); AMD provides an MXFP4 checkpoint ([amd/Qwen3.5-397B-A17B-MXFP4](https://huggingface.co/amd/Qwen3.5-397B-A17B-MXFP4)) for MI355X.
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- **B200 (183GB)** runs with tp=4. (NVFP4)
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- **B200 (183GB)** runs with tp=4. (NVFP4)
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- **B300 (275GB)** runs with tp=2. (NVFP4)
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- **B300 (275GB)** runs with tp=2. (NVFP4)
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- **MI355X (288GB)** runs with tp=2 (use tp=4 for low concurrency). (MXFP4)
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- **MI355X (288GB)** runs with tp=2 (use tp=4 for low concurrency). (MXFP4)
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@@ -318,10 +318,10 @@ export const Qwen35Deployment = () => {
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let modelName;
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let modelName;
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if (quantization === 'fp4') {
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if (quantization === 'fp4') {
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// AMD MI355X uses the MXFP4 checkpoint; Blackwell uses NVFP4.
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// AMD MI355X uses the MXFP4 checkpoint; Blackwell uses NVFP4-V2.
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modelName = hardware === 'mi355x'
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modelName = hardware === 'mi355x'
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? 'amd/Qwen3.5-397B-A17B-MXFP4'
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? 'amd/Qwen3.5-397B-A17B-MXFP4'
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: 'nvidia/Qwen3.5-397B-A17B-NVFP4';
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: 'nvidia/Qwen3.5-397B-A17B-NVFP4-V2';
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} else {
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} else {
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const suffix = MODEL_SUFFIX[model];
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const suffix = MODEL_SUFFIX[model];
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const quantSuffix = quantization === 'fp8' ? '-FP8' : '';
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const quantSuffix = quantization === 'fp8' ? '-FP8' : '';
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