[Fix]: exclude SM120 from attn-res TMA dispatch (#35361)
Co-authored-by: 1BIN4 <1741738350@qq.com> Co-authored-by: L-Ark <fliangae@connect.ust.hk> Co-authored-by: Chikati <jxudn@connect.ust.hk> Co-authored-by: mengzili <zilim@ust.hk>
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co-authored by
1BIN4
L-Ark
Chikati
mengzili
parent
628674a5c7
commit
0bda0b168a
@@ -8,7 +8,7 @@
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# fast — warp-specialized TMA kernel: cp.async.bulk producer +
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# fast — warp-specialized TMA kernel: cp.async.bulk producer +
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# online-softmax consumers over a double-buffered chunk ring, out
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# online-softmax consumers over a double-buffered chunk ring, out
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# norm fused, per-nvb tuned launch config, one persistent CTA per
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# norm fused, per-nvb tuned launch config, one persistent CTA per
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# SM. Taken on SM100+ with H=7168.
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# SM. Taken on SM100+ except SM12x with H=7168.
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# hip — single Triton kernel, everything in one launch; taken on ROCm
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# hip — single Triton kernel, everything in one launch; taken on ROCm
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# within its register budget.
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# within its register budget.
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# fused — Triton 2-kernel pipeline with full H-parallelism; the fallback
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# fused — Triton 2-kernel pipeline with full H-parallelism; the fallback
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@@ -33,15 +33,20 @@ _FAST_SUPPORTED = None
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_HIP_SHAPE_GATE = None
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_HIP_SHAPE_GATE = None
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def _supports_attn_res_tma(capability: tuple[int, int]) -> bool:
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"""Return whether the device is eligible for the TMA fast path."""
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major, _ = capability
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return major >= 10 and major != 12
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def _use_fast(hidden_size: int) -> bool:
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def _use_fast(hidden_size: int) -> bool:
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"""The TMA kernel needs SM100+ (tcgen05, cp.async.bulk) and its H=7168
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"""The TMA kernel needs SM100+ except SM12x (tcgen05, cp.async.bulk)
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template instantiation; everything else takes the triton pipeline."""
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and its H=7168 template; everything else takes the triton pipeline."""
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global _FAST_SUPPORTED
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global _FAST_SUPPORTED
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if is_npu():
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if is_npu():
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return False
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return False
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if _FAST_SUPPORTED is None:
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if _FAST_SUPPORTED is None:
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major, _ = torch.cuda.get_device_capability()
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_FAST_SUPPORTED = _supports_attn_res_tma(torch.cuda.get_device_capability())
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_FAST_SUPPORTED = major >= 10
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return _FAST_SUPPORTED and hidden_size == 7168
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return _FAST_SUPPORTED and hidden_size == 7168
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@@ -0,0 +1,20 @@
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import unittest
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from sglang.srt.layers.attn_residual import _supports_attn_res_tma
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from sglang.test.ci.ci_register import register_cpu_ci
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register_cpu_ci(est_time=5, suite="base-a-test-cpu")
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class TestAttnResidual(unittest.TestCase):
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def test_tma_capability_gate(self):
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self.assertFalse(_supports_attn_res_tma((9, 0)))
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self.assertTrue(_supports_attn_res_tma((10, 0)))
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self.assertTrue(_supports_attn_res_tma((10, 3)))
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self.assertTrue(_supports_attn_res_tma((11, 0)))
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self.assertFalse(_supports_attn_res_tma((12, 0)))
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self.assertTrue(_supports_attn_res_tma((13, 0)))
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if __name__ == "__main__":
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unittest.main()
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