diff --git a/test/registered/models/test_vit_pos_embed_interpolate.py b/test/registered/models/test_vit_pos_embed_interpolate.py
index ef9313797..05d2e086b 100644
--- a/test/registered/models/test_vit_pos_embed_interpolate.py
+++ b/test/registered/models/test_vit_pos_embed_interpolate.py
@@ -20,11 +20,16 @@ from types import SimpleNamespace
 import torch
 import torch.nn as nn
 
-from sglang.test.ci.ci_register import register_cpu_ci, register_cuda_ci
+from sglang.test.ci.ci_register import (
+    register_amd_ci,
+    register_cpu_ci,
+    register_cuda_ci,
+)
 from sglang.test.test_utils import CustomTestCase
 
 register_cpu_ci(est_time=20, suite="base-a-test-cpu")
 register_cuda_ci(est_time=20, stage="base-a", runner_config="1-gpu-small")
+register_amd_ci(est_time=20, stage="stage-a", runner_config="1-gpu-small-amd")
 
 NUM_POS = 2304  # Qwen3-VL num_position_embeddings -> 48x48 grid
 HIDDEN = 64  # small hidden dim keeps the unit test fast
diff --git a/test/registered/unit/mem_cache/test_minimax_sparse_pool_host_unit.py b/test/registered/unit/mem_cache/test_minimax_sparse_pool_host_unit.py
index c93336e1a..dca83fb35 100644
--- a/test/registered/unit/mem_cache/test_minimax_sparse_pool_host_unit.py
+++ b/test/registered/unit/mem_cache/test_minimax_sparse_pool_host_unit.py
@@ -19,9 +19,10 @@ from sglang.srt.mem_cache.pool_host.common import (
     alloc_with_pin_memory,
 )
 from sglang.srt.utils import is_cuda, is_hip, is_npu, is_xpu
-from sglang.test.ci.ci_register import register_cuda_ci
+from sglang.test.ci.ci_register import register_amd_ci, register_cuda_ci
 
 register_cuda_ci(est_time=9, stage="base-b", runner_config="1-gpu-small")
+register_amd_ci(est_time=9, stage="stage-b", runner_config="1-gpu-small-amd")
 
 
 def _cuda_major() -> int:
@@ -389,6 +390,13 @@ class TestMiniMaxSparseHiCacheTransfer(unittest.TestCase):
     def test_device_to_host_kernel_layer_first(self):
         self._run_device_to_host_copy(io_backend="kernel", layout="layer_first")
 
+    @unittest.skipIf(
+        is_hip(),
+        "ROCm sgl-kernel transfer_kv_all_layer_lf_pf requires a CUDA dst-indices "
+        "tensor for the kernel+page_first combo, while CUDA accepts the CPU "
+        "dst-indices this combo feeds. The production io_backend=kernel + "
+        "layer_first path is covered by test_device_to_host_kernel_layer_first.",
+    )
     def test_device_to_host_kernel_page_first(self):
         self._run_device_to_host_copy(io_backend="kernel", layout="page_first")