[NPU] [FIX] Fix performance degradation of Qwen3.5-397B-A17B (#32130)
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@@ -265,22 +265,13 @@ class AscendHybridLinearAttnBackend(HybridLinearAttnBackend):
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last_steps = last_correct_step_indices.to(torch.int64) # [N]
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last_steps = last_correct_step_indices.to(torch.int64) # [N]
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# NPU: skip intermediate_ssm copy when accept_lens == 1.
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move_intermediate_cache(
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# The state at step 0 is the just-computed recurrent state, which
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ssm_states,
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# is already correct in the model's ssm buffer. The intermediate
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intermediate_state_cache,
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# cache path exists for CUDA's per-step gather; on NPU the fused
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dst_indices_tensor,
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# kernel may produce slightly different bfloat16 rounding that
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src_indices_tensor,
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# accumulates over thousands of decode steps and drifts into
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last_steps,
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# garbage output.
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)
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all_step0 = (last_steps == 0).all().item()
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if not all_step0:
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move_intermediate_cache(
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ssm_states,
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intermediate_state_cache,
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dst_indices_tensor,
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src_indices_tensor,
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last_steps,
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)
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draft_token_num = intermediate_state_cache.shape[2]
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draft_token_num = intermediate_state_cache.shape[2]
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if mamba_track_indices is not None:
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if mamba_track_indices is not None:
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